Value Proposition - Increased Yields

STS has deep, determined, and well rounded expertise and partnerships in all significant disciplines of yield improvement to accelerate your yield learning curve at any stage of the product life cycle and significantly improve your margins. We also know what your yield entitlement should be, and can benchmark your product families against this.

Our seasoned team will evaluate your present yield and historical learning curve against the technology and design complexity entitlement of your product, and perform deep-dive analysis and data mining of your test and manufacturing information to find low hanging fruit for quick yield gains. If needed, we will perform fault localization and root cause failure analysis to determine and feed back physical causes, along with recommendations to eliminate or improve yield loss from these causes.

We have deep knowledge and experience in:

  • Product characterization and corners analysis
  • Product debug
  • Test debug
  • Design-for-test and design-for-manufacturability implementation
  • Yield modeling
  • Test and manufacturing data analysis and data mining
  • Wafer fabrication modules and flows
  • Fault localization
  • Physical and electrical failure analysis
  • Defect analysis and reduction
  • Test chip design, test and analysis
  • Assembly and final test yield loss mechanisms

on analog, mixed-signal, SoC, and embedded memory products on any silicon technology. Our experience also spans complex packaging solutions including single, multi-chip, and 3D integration.

Specific STS yield improvement services include:

STS puts you on a world-class yield curve, fast.


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